1. Field of the Invention
The present invention pertains to a method of controlling an analog-to-digital (AD) converter. More particularly, it relates to a method of controlling an AD converter formed on a semiconductor substrate and implemented in a semiconductor integrated circuit.
2. Description of the Prior Art
Referring now to FIG. 18, there is illustrated a block diagram showing the structure of a successive approximation 4-bit AD converter having a sample-and-hold function, to which a prior art AD converter controlling method as disclosed in, for example, Japanese Patent Application Laying Open No. 1-321728, is applicable. In the figure, reference numeral 1 denotes a control circuit, 2 denotes a successive approximation register holding digital data furnished by the control circuit 1, 3 denotes a resistor ladder, 4 and 5 denote power supply terminals for applying a basic voltage V, which is equal to a maximum of voltages which can be converted by the AD converter, across the resistor ladder 3, and 6 denotes a switch group comprised of switches for selecting, as a reference voltage Vref, one from among a plurality of voltages generated by the resistor ladder 3 according to a data furnished by the successive approximation register 2. The resistor ladder 3 and the switch group 6 serve as a digital-to-analog (DA) converter for digital-to-analog converting a digital data furnished by the control circuit 1 into the reference voltage Vref.
Furthermore, reference numeral 7 denotes an input terminal to which an input voltage Vin is applied, 8 denotes a capacitor, and 9 denotes an inverter. The capacitor 8 and the inverter 9 form a chopper comparator for comparing the input voltage Vin to the reference voltage Vref in cooperation with each other. Reference numeral 10 denotes a first switch, 11 denotes a second switch, 12 denotes a third switch, and 13 denotes a timing generator for generating a timing pulse to turn on or off each of the switches 10 to 12, and a timing pulse to trigger the successive approximation register 2 to furnish a data stored therein to the switch group 6.
Referring next to FIG. 20, there is illustrated a timing diagram for explaining the operation of the prior art method of controlling the AD converter shown in FIG. 18. FIG. 20 shows the case where a voltage of 0.63 volts which is 0.63 times the basic voltage V, as the input voltage Vin, is applied to the input terminal 7. The timing generator 13 generates a timing pulse to turn on the first switch 10 first, and, after that, the timing generator 13 further generates a timing pulse to trigger the successive approximation register 2 to furnish data held therein to the switch group 6. A hexadecimal number such as "8h" is delivered to the switch group first by the successive approximation register 2. According to the data, the switch group 6 furnishes the reference voltage Vref of 1/2 V which is generated by the resistor ladder 3. The resistor ladder 3 divides the basic voltage V into a plurality of voltages Vi (i=1 to n). Thus, the switch group 6 selects, as the reference voltage, one from among the plurality of voltages Vi generated by the resistor ladder 3 according to the digital data from the successive approximation register 2.
Then the timing generator 13 generates a timing pulse to turn on the third switch 12 so as to raise a condition in which the capacitor 8 can become charged. Furthermore, the timing generator 13 generates a timing pulse to turn on the second switch 11 so as to charge the capacitor 8 with the input voltage Vin applied to the input terminal 7. When the capacitor 8 becomes charged, the second and third switches 11 and 12 are turned off sequentially, and the first switch 10 is further turned on. When the first switch 10 is switched on, the reference voltage Vref furnished by the switch group 6 is applied to the capacitor 8 and is compared with the input voltage Vin. In this case, since the input voltage Vin is 0.63 V and the reference voltage is 1/2 V, the inverter 9 outputs a signal having a value of zero.
When the control circuit 1 receives the signal at a logical state 0 from the inverter 9, it changes the digital data delivered to the successive approximation register to a hexadecimal number "Ch". The new digital data is furnished to the switch group 6 by way of the successive approximation register 2. Then the switch group 6 selects and furnishes the new reference voltage Vref of (3/4) V according to the digital data applied thereto. As shown in FIG. 20, since the first switch 10 had been already turned on and the second and third switches 11 and 12 had been already turned off when the capacitor 8 became charged with the reference voltage at the first time, it is not necessary to repeat the turning-on/off operation on the first, second, and third switches 10 to 12 after the first reference voltage Vref has been applied to the capacitor. Thus, the first switch 10 remains in the on state and the second and third switches 11 and 12 remain in the off state, and therefore the selected reference voltage Vref of 3/4 V is applied to the capacitor 8 by way of the first switch 10 and is compared with the input voltage of 0.63 V. As a result, the inverter 9 outputs a signal at a logical state 1. After that, the AD converter repeats a similar control operation, and, finally, furnishes a hexadecimal number "Ah" as a conversion result.
When the control circuit 1 determines a new digital data to be furnished to the switch group 6 by way of the successive approximation register 2, one switch of the switch group 6 changes from the on state to the off state and another switch of the switch group 6 changes from the off state to the on state. This switching operation causes the reference voltage Vref furnished by the switch group 6 to make a transition to a new value under the control of the switch group 6, as shown in FIG. 20. That is, the reference voltage Vref remains in an unstable state during the transition. Thus, when obtaining a second or later bit of the digital data, since the output of the successive approximation register 2 changes while the first switch 10 is held in the on state and the second and third switches 11 and 12 are held in the off state, there is a possibility that a comparison between the input voltage Vin and the reference voltage Vref which remains in an unstable state is performed. Such a change in the reference voltage Vref which is making a transition to a new value, which has been caused by the tap changing of the resistor ladder 3, under the control of the switch group exerts a bad influence upon the conversion accuracy of the AD converter.
A capacitance-coupled AD converter has been controlled by using a controlling method similar to the aforementioned prior art AD converter controlling method for use in a successive approximation AD converter having a sample-and-hold function. Next, the description will be directed to the prior art method of controlling a capacitance-coupled AD converter.
Referring next to FIG. 19, there is illustrated a block diagram showing the structure of an 8-bit capacitance-coupled AD converter to which the prior art AD converter controlling method is applicable. In the figure, the same components as the AD converter shown in FIG. 18 are designated by the same reference numerals, and therefore the description about the components will be omitted hereinafter. In FIG. 19, reference numeral 14 denotes a second capacitor, 15 denotes a base terminal to which a basic potential such as an analog basic potential AVSS is applied, and 16 denotes a switch group comprised of a plurality of switches, which is different from the switch group 6 shown in FIG. 18 in that the switch group 16 can furnish a first reference voltage Vref used for a comparison to be performed for obtaining the five uppermost bits of a conversion result and a second reference voltage Vref used for a comparison to be performed for obtaining the three lowermost bits of the conversion result, separately. Furthermore, reference numeral 17 denotes a fourth switch, and 18 denotes a fifth switch. A semiconductor switch such as a field-effect transistor analog switch can be used as each of the switches, which can be turned on or off in response to a timing pulse generated by the timing generator 13.
Referring next to FIG. 21, there is illustrated a timing diagram for explaining the operation of the prior art method of controlling the capacitance-coupled AD converter shown in FIG. 19. Such the capacitance-coupled AD converter has been developed as a technique for improving the conversion accuracy when it is used in the case where the number of bits of a digital data to be obtained is relatively large. The 8-bit capacitance-coupled AD converter shown in FIG. 19 can separately perform AD conversions for the five uppermost bits and three lowermost bits of the conversion result. When charging the first capacitor 8 and the second capacitor 14, the first switch 10, second switch 11, third switch 12, fourth switch 17, and fifth switch 18 are sequentially turned on and off with timing as will be mentioned below. After that, these switches do not repeat the turning on/off operation. To be more specific, when converting the input voltage Vin into digital data, the first and fourth switches 10 and 17 are turned off first. Then the third, second, and fifth switches 12, 11, and 18 are turned on. As a result, the first and second capacitors 8 and 14 become charged. When the charging is completed, the second, third, and fifth switches 11, 12, and 18 are turned off and, after that, the first and fourth switches 10 and 17 are turned on. Then an AD conversion is started.
When comparisons for obtaining the uppermost bits of the conversion result are started, the reference voltage Vref furnished by the switch group 16 is applied to the first capacitor 8 by way of the first switch 10 which remains in the on state. Furthermore, during the comparison carried out to obtain each of the uppermost bits of the conversion result, the switch group 16 constantly supplies a constant voltage of 0 V to the second capacitor 14 by way of the fourth switch 17 which remains in the on state. The inverter 9 compares the reference voltage Vref with the sum of the charged voltages across the first and second capacitors 8 and 14, and then furnishes its output having a value which depends on the comparison result to the control circuit 1. The control circuit 1 determines new digital data to be delivered to the successive approximation register according to the value of the output of the inverter. The reference voltage Vref to be furnished to the first switch 10 by the switch group 16 is thus changed according to the new digital data from the successive approximation register. At that time, since the first switch 10 is held in the on state, the reference voltage Vref is applied to the first capacitor 8 and therefore the inverter 9 furnishes its output having a value which depends on the comparison between the reference voltage Vref and the sum of the charged voltages across the capacitors 8 and 14 to the control circuit 1. After that, a further AD conversion operation is similarly carried out to obtain the remainder of the five uppermost bits of the conversion result.
When the comparisons for obtaining the five uppermost bits are completed, the AD converter shifts to comparisons for obtaining the three lowermost bits of the conversion result. After the comparisons for the lowermost bits are started, the reference voltage Vref furnished by the switch group 16 is applied to the second capacitor 14 by way of the fourth switch 17 which remains in the off state. During the comparison for obtaining each of the lowermost bits, a voltage having a value which corresponds to binary data comprised of the five uppermost bits fixed as mentioned above and the three lowermost bits each set to 0, which will be referred to as a final value, is constantly applied to the first capacitor 8 by way of the first switch 10 which remains in the on state. The inverter 9 compares the sum of the voltage having the final value and the reference voltage Vref with the sum of the charged voltages across the first and second capacitors 8 and 14. Then the inverter furnishes its output having a value which depends on the comparison result to the control circuit 1. The control circuit 1 determines new digital data to be delivered to the successive approximation register according to the value of the output of the inverter. The reference voltage Vref to be furnished to the fourth switch 17 by the switch group 16 is thus changed according to the new digital data from the successive approximation register. At that time, since the fourth switch 17 is held in the on state, the reference voltage Vref is applied to the second capacitor 14 and therefore the inverter 9 furnishes its output having a value which depends on the comparison between the sum of the voltage having the final value and the reference voltage Vref and the sum of the charged voltages across the capacitors 8 and 14 to the control circuit 1. After that, a further AD conversion operation is similarly carried out to obtain the remainder of the three lowermost bits of the conversion result.
The reference voltage Vref which is generated by the resistor ladder 3 and is selected by the switch group 6 is thus injected to the inverter 9 during the comparison for the uppermost and lowermost bits. Therefore, in either case, since the first and fourth switches 10 and 17 remain in the on state, the unstable reference voltage Vref which is making a transition from the previous value to a new value under the control of the switch group 16, is applied, by way of either the first switch 10 or the fourth switch 17, to the first capacitor 8 or the second capacitor 14 and hence to the input of the inverter 9. Thus, the unstable reference voltage Vref which is changing to a new value under the control of the switch group 16 exerts a bad influence upon the conversion accuracy of the AD converter.
Thus, a problem with the prior art method of controlling an AD converter which is so implemented as mentioned above is that in the case where the method is used for a successive approximation AD converter having a sample-and-hold function, since the AD converter controls the switch group 16 which selects, as the reference voltage Vref, one from among a plurality of voltages into which the voltage V between the terminals 4 and 5 is divided by the resistor ladder 3, with the first switch 10 held in the closed state, the conversion accuracy of the AD converter is decreased due to the unstable reference voltage furnished by the switch group 16 which is making a transition to a new value under the control of the switch group. As previously explained, when starting an AD conversion, the first to third switches 10 to 12 operate sequentially with predetermined timing so that the capacitor 8 is charged with the input voltage Vin. Then, the AD converter turns off the second and third switches 11 and 12 sequentially, and further turns on the first switch 10. After that, the AD converter does not repeat such the turning on/off operation. The unrepeatable switching operation has made it difficult to fix the above problem.
Similarly, in the case of controlling a capacitance-coupled AD converter, the prior method suffers from the same drawback that since both the first and fourth switches 10 and 17 are held in the closed state when conducting comparisons for the uppermost and lowermost bits, the conversion accuracy of the AD converter is decreased due to the unstable reference voltage Vref furnished by the switch group 16 which is changing to a new value under the control of the switch group 16.